SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. IC LAYOUT ENGINEER (STARLINK) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to 1.5M+ users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry) Work with EDA suppliers to trial new tools and features Generate guides and demos for others in the team to showcase improvements in layout technique BASIC QUALIFICATIONS: Bachelor's degree in electrical or computer engineering 1+ years of professional experience as an IC layout designer OR 3+ years of professional experience with integrated circuit layout design PREFERRED SKILLS AND EXPERIENCE: Strong analog layout skills Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below Experience in layout of circuits with frequencies up to 50GHz Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers Experience with skill programming Experience with shell scripting, Perl, Python or similar language Experience managing revision control systems Experience with circuit design Understanding of layout considerations for device matching, coupling and noise isolation Working knowledge of Linux Excellent communication skills (both oral and written) are required Able to work independently on challenging problems ADDITIONAL REQUIREMENTS: Must be willing to work extended hours and weekends as needed to meet critical milestones COMPENSATION AND BENEFITS: Pay range: Silicon Engineer/Level I: $120,000.0